# EDAPack top-level package catalog
#
# Published at the web root: https://edapack.github.io/ivpm.yaml
#
# Structure:
# - Each tool has its own single-package dep-set so it can be pulled
#   individually (e.g. `ivpm update --from <this> -d verilator`).
# - Collections are curated multi-tool bundles for common workflows. They are
#   defined by reference: `uses:` lists the package dep-sets they bundle, so
#   each tool's source URL is declared exactly once (above) and never repeated.
#   Collections are named with a category prefix (sim.*, flow.*, verif.*,
#   embedded.*) so related bundles group together. Overlapping packages
#   (e.g. yosys) are deduplicated by IVPM.
#
# Every package is sourced from its GitHub binary releases (src: gh-rls) and
# cached locally.

package:
  name: edapack
  description: Catalog of prebuilt open-source EDA tools, installable individually or as curated workflow collections via IVPM

  dep-sets:

  # ---- Packages ------------------------------------------------------------
  # One dep-set per tool; the single source of truth for each tool's release
  # URL. Collections below reference these by name.

  - name: gcc-riscv
    description: GNU C/C++ cross-compiler toolchain targeting RISC-V
    deps:
    - name: gcc-riscv
      url: https://github.com/edapack/gcc-riscv-bin
      src: gh-rls
      cache: true

  - name: gdb-multiarch
    description: GNU debugger with multi-architecture support (incl. RISC-V)
    deps:
    - name: gdb-multiarch
      url: https://github.com/edapack/gdb-multiarch-bin
      src: gh-rls
      cache: true

  - name: icestorm
    description: Bitstream tools and chip database for Lattice iCE40 FPGAs
    deps:
    - name: icestorm
      url: https://github.com/edapack/icestorm-bin
      src: gh-rls
      cache: true

  - name: iverilog
    description: Icarus Verilog event-driven Verilog simulator and synthesizer
    deps:
    - name: iverilog
      url: https://github.com/edapack/iverilog-bin
      src: gh-rls
      cache: true

  - name: nextpnr
    description: Portable FPGA place-and-route tool
    deps:
    - name: nextpnr
      url: https://github.com/edapack/nextpnr-bin
      src: gh-rls
      cache: true

  - name: ngspice
    description: SPICE analog/mixed-signal circuit simulator
    deps:
    - name: ngspice
      url: https://github.com/edapack/ngspice-bin
      src: gh-rls
      cache: true

  - name: openroad
    description: RTL-to-GDS digital place-and-route and physical design flow
    deps:
    - name: openroad
      url: https://github.com/edapack/openroad-bin
      src: gh-rls
      cache: true

  - name: opensta
    description: OpenSTA gate-level static timing analyzer
    deps:
    - name: opensta
      url: https://github.com/edapack/opensta-bin
      src: gh-rls
      cache: true

  - name: qemu-riscv
    description: QEMU emulator for running and debugging RISC-V binaries
    deps:
    - name: qemu-riscv
      url: https://github.com/edapack/qemu-riscv
      src: gh-rls
      cache: true

  - name: verilator
    description: Verilator high-performance Verilog/SystemVerilog-to-C++ simulator
    deps:
    - name: verilator
      url: https://github.com/edapack/verilator-bin
      src: gh-rls
      cache: true

  - name: yosys
    description: Yosys RTL synthesis framework for Verilog
    deps:
    - name: yosys
      url: https://github.com/edapack/yosys-bin
      src: gh-rls
      cache: true

  # ---- Collections ---------------------------------------------------------
  # Curated multi-tool bundles, defined by reference to the packages above.

  - name: sim.rtl
    description: Verilog/SystemVerilog RTL simulation (Verilator + Icarus Verilog)
    uses: [verilator, iverilog]

  - name: sim.analog
    description: SPICE analog/mixed-signal simulation (ngspice)
    uses: [ngspice]

  - name: flow.fpga.ice40
    description: Open bitstream flow for Lattice iCE40 FPGAs (Yosys + nextpnr + IceStorm)
    uses: [yosys, nextpnr, icestorm]

  - name: flow.asic
    description: Digital RTL-to-GDS ASIC flow — synthesis, place-and-route, static timing (Yosys + OpenROAD + OpenSTA)
    uses: [yosys, openroad, opensta]

  - name: verif.formal
    description: Formal verification backend (Yosys; pairs with SymbiYosys + solvers)
    uses: [yosys]

  - name: embedded.riscv
    description: RISC-V bare-metal development — toolchain, debugger, emulator (gcc-riscv + gdb-multiarch + qemu-riscv)
    uses: [gcc-riscv, gdb-multiarch, qemu-riscv]